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Sample VLSI interview questions and answers for a fresher Part-2

3 Comments

Continuing from Part -1

9) What are the different logic families ? Compare between them.

10) If both of the below circuits should give the same output, what should be the order of the input in the second circuit?

Ans:

VLSI INTERVIEW QUESTIONS

VLSI INTERVIEW QUESTIONS

 

 

 

 

11) See the piece of RTL code below                                                                          

process (A)                                                                              

begin                                                                                    

C = A and B

end                                                                                      

end process                                                                              

The input changes are as given below. What is the output.                                

A           B               C


0            0               ?


0           1               ?                                                          

1           0               ?                                                          

1           1               ?        


Ans: Since only A is there in the process sensitivity list, the output changes only when there is a change in A input ie    

A                    B                    C  

0                    0                     0                                             

0                    1                     0                                            

1                    0                     0                                              

1                    1                     0


12)Draw the output of the below circuit, suppose I is at 0 initially. tpd is the delay of the inverter.

VLSI INTERVIEW QUESTIONS

 

 

 

 

Ans:

VLSI INTERVIEW QUESTIONS

 

 

 

 

13) Draw the basic circuit of a D Flip Flop ?

Ans) Please refer my earlier post ” Latch vs Flip Flop“.

14)Write the equation for drain current of CMOS transistor.

Ans) Kindly refer my earlier post on ” CMOS basics“.

15) Design a NOT gate using a NAND gate.

Ans:

VLSI INTERVIEW QUESTIONS 

 

 

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  • Manohar

    Hello Mam,
    I have a question regarding setting the constraints.
    Suppose we have a constraint file defined with input and output delay for a particular operating frequency…Now i reduce my frequency, how do we scale down the constraints based on that frequency ?

    This is wat i have understood till now, since the frequency has reduced that means time period has increased, so the input and output delay defined previously may not hold good rite ? [ The input and output delays have to be increased rite ?]

    On what basis do we scale the constraints for the new frequency ?

    Please help me out with this…

  • tdzire

    Hi Manohar,

    Input/output delays are generally
    defined as a particular percentage of the clock period. Generally it is
    60%. I will give an example. Suppose you are using Synopsys tools.
    The clock period is 10 ns, ie frequency 100 Mhz. The input/output delay is
    6 ns. Thus it is defined as

    set_input_delay 6 -clock [get_ports ]

    The 6 ns here means that the outside world will take 6 ns delay. So inside
    your chip, you have only 4 ns to meet the path.

    Yes, When you change the clock frequency, you need to change the input/output delays.I suggest you to see, what percentage of the clock is defined as input/output delay and change it accordingly for the new clock frequency.

    Gayathri

    • Manohar

      Hi,
      Thank You 🙂 Got the Point.